In deep sub-micron integrated circuit technology, an embedded static random access memory (SRAM) device has become a popular storage unit of high speed communication, image processing and system-on-chip (SOC) products. The amount of embedded SRAM in microprocessors and SOCs increases to meet the performance requirement in each new technology generation. As silicon technology continues to scale from one generation to the next, the impact of intrinsic threshold voltage (Vt) variations in minimum geometry size bulk planar transistors reduces the complimentary metal-oxide-semiconductor (CMOS) SRAM cell static noise margin (SNM). This reduction in SNM caused by increasingly smaller transistor geometries is undesirable. SNM is further reduced when Vcc is scaled to a lower voltage.
To solve SRAM issues and continue to improve cell shrink capability, the fin field effect transistor (FinFET) devices are often considered for some applications. The FinFET provides both speed and device stability. The FinFET has a channel (referred to as a fin channel) associated with a top surface and opposite sidewalls. Benefits can be provided from the additional sidewall device width (Ion performance) as well as better short channel control (sub-threshold leakage). In FinFet cell devices, the setting of single fin cell device faces cell ratio problems like beta ratio (Ipd/Ipg) or alpha ratio (Ipu/Ipg). One important parameter of cell stability is referred to as “beta ratio” and is defined as the ratio between pull-down transistor drive current and pass-gate transistor drive current. A high beta ratio greater than 1 is desired in order to improve the stability of the SRAM cell. SRAM cell voltage Vcc_min is a factor related to the write capability. The corresponding parameter is the ratio between pull-up transistor drive current and pass-gate transistor drive current, referred to as “alpha ratio.” Hence, in order to increase electrical current in a given cell area, the pitch between the fins has to be minimized. Unfortunately, it is difficult to achieve further reductions in pitch in FinFET devices, due to fundamental limitations in existing lithography techniques (like tight pitch fin nodes connection and contact to contact space rule).
Therefore, there is a need of new structure and method for SRAM cells to address these concerns for high-end cell application and improved multiple fins cell size.